Tutorial on Analog In-Memory Computing Circuits: Systematization of Computation Principles, Non-idealities, and Hardware-Aware Training

A research team led by Yusuke Sakemi, Hiromitsu Awano, and Takashi Morie has published an invited tutorial paper on Analog In-Memory Computing (AIMC), a promising technology for next-generation, ultra-low-power AI hardware. To reduce the significant power consumption from data movement between processors and memory in AI tasks, AIMC performs computations directly within the memory array. The paper's main contributions are threefold: (1) it classifies AIMC's matrix-vector multiplication methods into six memory-agnostic types, such as current-domain and charge-domain; (2) it categorizes the non-idealities inherent in analog computation into device-induced and circuit-structure-induced issues; and (3) it systematizes Hardware-Aware Training (HAT) techniques into three approaches to mitigate these non-idealities. This comprehensive framework facilitates a deeper understanding of existing research and provides a guide for developing future energy-efficient edge AI hardware.