Intel Aims to Disrupt HBM? XBM Memory Revealed, Promising Major Cost Reduction in Packaging

As the era of artificial intelligence (AI) continues to drive demand for high-bandwidth memory (HBM), a recently revealed patent from Intel (INTC-US) has unveiled a new alternative architecture called Cross-Batch Memory (XBM), aiming to overcome current limitations of HBM in packaging cost and scalability.

According to a report by Tom’s Hardware, independent tech analyst Underfox revealed that Intel publicly filed a patent application on July 2, 2026, describing a new ultra-high-bandwidth memory architecture named Cross-Batch Memory (XBM).

The patent was actually filed earlier on December 26, 2024, with the core goal of reducing packaging costs and improving manufacturing yield by introducing a new memory process and interconnect method, all while maintaining the same package size as HBM4.

Current HBM achieves extremely high bandwidth by vertically stacking multiple DRAM chips and connecting them to GPUs or AI accelerators via a ~1,024-bit ultra-wide parallel interface using through-silicon vias (TSV) and silicon interposers.

However, while this design delivers excellent performance, it also brings high packaging costs and complex routing requirements. As AI chips grow larger, the 'memory wall' is increasingly becoming the biggest bottleneck for overall computing performance.

Intel’s proposed XBM changes this architecture fundamentally.

The first major change lies in structural design. In traditional DRAM, memory cells are built in the front-end-of-line (FEOL) process—the base silicon layer where transistors are typically fabricated.

XBM, however, adopts thin-film transistors (TFT), relocating the 1T1C (one transistor, one capacitor) memory cells to the back-end-of-line (BEOL) process—the stack of metal interconnects and vias located above the transistor layer.

By constructing memory in the BEOL, Intel can divide the die into numerous small memory blocks that can be independently addressed. This continues Intel’s recent technological direction of using BEOL transistors to stack memory directly on top of logic circuits.

The second change is in the interface design. Instead of HBM’s ultra-wide parallel physical-layer interface, XBM serializes data and transmits it via UCIe (Universal Chiplet Interconnect Express) links operating at up to 32 GT/s. A base die handles serialization/deserialization and routes all I/O signals to the compute die.

By adopting a standardized chiplet interconnect interface, XBM becomes a truly chiplet-native architecture. Intel believes this design can significantly simplify the packaging process and reduce costs compared to HBM stacks that rely on silicon interposers.

However, a drawback is that 32 GT/s is already the maximum data rate supported by current UCIe specifications, meaning the interface starts near the upper limit of the spec, leaving limited room for future performance improvements.

Intel also emphasizes XBM’s repairability. The base die includes dedicated redundant channels, built-in self-repair mechanisms, decode and debug logic, and four sub-channels composed of redundant memory arrays that can serve as replaceable backup resources when defects occur in the upper memory layers.

This post-packaging repair capability is designed to improve the overall yield of high-layer-count memory stacks.

A significant portion of the patent application focuses not on the memory cells themselves, but on packaging and mounting methods. Intel details packaging structures such as Memory-on-Package (MoP) and 'reverse overhang,' aiming to reduce the Z-axis height of memory stacks. For comparison, traditional MoP packaging typically adds about 300 to 350 micrometers in height.

Additionally, the new design eliminates the reinforcement frame previously required to suppress package warping and instead uses voltage regulators to directly power the DRAM. These design choices form the technical foundation for Intel’s claim of achieving a 'smaller, cheaper package.'

However, analysts caution against conflating XBM with ZAM (Z-Angle Memory). ZAM is a next-generation memory architecture jointly developed by Intel and SAIMEMORY, a subsidiary of SoftBank, expected to be presented at the 2026 VLSI Symposium.

ZAM’s innovation centers on chip bonding technology, using fusion bonding to create a nine-layer stacked structure, with layers separated by ultra-thin silicon layers approximately 3 micrometers thick. The memory itself largely follows traditional DRAM design.

Reports suggest ZAM aims to achieve about twice the bandwidth density of HBM4 and is expected to be commercialized around 2029.

In contrast, XBM is a patent independently filed by Intel, not only repositioning the DRAM transistors themselves but also completely overhauling the interconnect interface between memory and compute dies.

Viewing both technologies together, it’s clear Intel is simultaneously advancing at least two distinct next-generation HBM technology paths. For a company that started in memory in 1968, this strategy is not surprising.

However, XBM remains at the patent stage. Intel has not announced any related products or roadmaps, so for now, it appears more as a demonstration of technological positioning and R&D direction rather than an imminent product launch.

Moreover, the UCIe interface is already at the maximum supported speed under current specifications, and DRAM using BEOL transistors has yet to prove its viability for mass production. The overall architecture must still demonstrate whether it offers sufficient competitive advantage over HBM4E and Intel’s own ZAM technology path.