As Moore's Law approaches physical limits and advanced manufacturing processes face restrictions, Huawei has released a 'Tao Law' (τ-Law) V2 paper, introducing a new technical pathway for what the industry calls an 'explosive upgrade' of 5nm chips. This approach no longer relies on geometric scaling but instead restructures chip design through 'time scaling,' extracting higher performance from existing 5nm chips, positioning it as a key direction for overcoming chip bottlenecks in the post-Moore era.

For decades, semiconductor industry evolution has centered on geometric scaling—doubling transistor density every two years. However, due to strict U.S. export bans on advanced EUV lithography equipment, Huawei has faced significant constraints in process node advancement.

Unable to shrink chip sizes through traditional means, Huawei proposed the 'Tao Law,' which centers on the circuit signal switching time constant (τ).

This theory posits that the essence of chip performance lies in signal transmission and processing time, with geometric scaling being just one tool for compressing time.

By systematically reducing τ values and conducting full-stack optimization—from transistors and circuits to chips and systems—Huawei skillfully circumvents over-reliance on cutting-edge lithography equipment, demonstrating exceptional mastery of system engineering.

Squeezing Peak Performance from Fixed Nodes

'Logic Folding,' the key technology enabling the practical application of 'Tao Law,' fundamentally restructures the chip's physical architecture.

Traditional chip design typically uses a planar (2D) layout, whereas Logic Folding is akin to shifting from a single-story house to a vertically stacked high-rise building. It stacks circuits along the Z-axis and replaces lengthy planar wiring with high-efficiency inter-layer connections such as TSV technology.

The upcoming Kirin 2026 chip, set to debut this autumn, will be the first mass-produced validation of this technology.

According to Huawei's paper, under fixed process nodes, this technology enables a dramatic leap in transistor density. The performance gains and power efficiency improvements rival—and in some scenarios surpass—those achieved through traditional generational process advancements.

This breakthrough proves that, through architectural innovation, even chips based on older nodes can be 'radically upgraded' to deliver powerful computing capabilities.

Addressing Post-Moore Era Challenges

The release of 'Tao Law' V2 is not merely a theoretical supplement but also a culmination of Huawei's six years of practical experience in mass-producing 381 chip models. This substantial engineering data robustly counters industry skepticism about the feasibility of its theory.

As tech giants like Apple shift toward STCO (System-Technology Co-Optimization), Huawei's Tao Law resembles an upgrade race in system engineering. It not only unifies goals between process and architecture designers but also expands optimization to memory hierarchy and computing architecture, ensuring the reduction of the system-wide τ value.

Huawei's move aims to break free from single-point technological constraints and establish a self-sustaining ecosystem that evolves continuously from fundamental devices to upper-layer algorithms.

Future Outlook of the 'Huawei Path'

Huawei's series of technological moves represent more than just a single company's technical evolution—they carry strong industrial strategic signals. While experts note that matching TSMC's latest process in absolute performance remains challenging in the short term, Tao Law opens a viable path for 'changing the race track.'

Through this theory, Huawei projects that by 2031, its high-end chips could achieve performance levels equivalent to 1.4nm processes. This not only alleviates current supply chain anxieties but also provides the Chinese semiconductor industry with a replicable 'design manual.'

In the long-term game of blockade and counter-blockade, Huawei has torn open a crack in the high wall of technology by 'radically upgrading' existing processes, offering a new possibility for chip development in the post-Moore era and creating subtle yet profound ripples in the global semiconductor landscape.

FACT BOX

  • Source: PR Times
  • Category: New Product