Advancing AI 2026 Kicks Off in San Francisco! AMD Challenges NVIDIA with Full-Stack 2nm Chips, Helios Rack, and Physical AI Vision

The annual AMD Advancing AI 2026 event kicked off on Thursday (23rd) in San Francisco, USA. Chair and CEO Lisa Su opened with a bold statement: 'AI is the most important technology in the past 50 years, and the industry has moved from chatbots into the era of Agentic AI.'

At the event, AMD launched its sixth-generation EPYC 'Venice' server CPU, Instinct MI400 series GPUs—including the flagship MI455X—Helios rack-scale AI infrastructure, and the Ryzen AI Embedded X100 and Kria AI platform for robotics and edge applications, completing a full-stack offensive from chip to software to rack.

Su projected that the AI accelerator market will reach $1.4 trillion by 2030, with the overall high-performance computing (HPC) market at $2 trillion, and the data center CPU segment valued at $220–230 billion.

She emphasized that Agentic AI tasks—orchestration, sandbox execution, and I/O coordination—still heavily rely on CPUs. The CPU-to-GPU ratio in AI servers has rebounded from 1:4 in the chatbot era to 1:1, which is why AMD continues to push high-core-count EPYC processors.

Citing internal data, Su noted that EPYC now holds a 46% revenue share in the server CPU market, a massive leap from near-zero a decade ago. AMD believes future competition lies not in individual chips, but in rack-level system integration encompassing 'CPU + GPU + networking + cooling + power.'

The sixth-generation EPYC 'Venice' (EPYC 9006 series) uses a 2nm GAA process from TSMC for compute dies and a 6nm I/O die, making it the industry's first 2nm x86 server processor. The flagship Venice model, based on the Zen 6c architecture, features up to 256 cores and 512 threads, 1152MB of L3 cache (with 3D V-Cache option), supports 16-channel DDR5 (up to 8000 MT/s) or MRDIMM (12800 MT/s), PCIe Gen 6, CXL 3.1, and fifth-gen Infinity Fabric. The Zen 6 variant targets high single-thread performance, while the Verano variant with LPDDR5X SOCAMM targets AI master nodes.

According to AMD, Venice delivers approximately twice the integer throughput of Intel's Xeon 6980P in SPECrate, with about 1.3x better single-core performance, maintaining an edge over Arm AGI competitors.

AMD claims Venice outperforms NVIDIA's Vera CPU by about 20% in overall performance. Venice is already in mass production, with systems expected to ship at scale in Q4 2026.

On the GPU front, the flagship is the Instinct MI455X, based on CDNA 5 architecture, built on TSMC's 2nm process with advanced packaging (CoWoS-L). It packs 320 billion transistors per card, 432GB of HBM4 (23.3 TB/s bandwidth)—a 1.5x capacity and ~2.9x bandwidth increase over the previous MI355X's 288GB HBM3E.

In MXFP4/MXFP8 formats, peak compute reaches 4x that of MI355X, with ~40 PFLOPS in FP4 and ~20 PFLOPS in FP8. Scale-up via UALoE delivers 3.6 TB/s per card, while scale-out via Pensando Vulcano 800G AI-NIC offers 600 GB/s, supporting up to 72 cards in a non-blocking pod.

The MI430X series targets HPC and sovereign AI, retaining FP64 scientific computing performance (up to 288 TFLOPS).

According to AMD's GPU roadmap, MI500 (CDNA 6) will launch in 2027, followed by MI600 (CDNA 7) in 2028.

The true highlight of the event was the Helios rack-scale solution, built on the OCP Open Rack Wide specification (1.2m wide, 44 OU). It features 18 compute trays, each with 4 MI455X GPUs and 1 Venice CPU, for a full configuration of 72 GPUs and 18 CPUs. Fully liquid-cooled, it consumes 225–245kW per rack, priced at $5–5.5 million. A single rack delivers 2.9 EFLOPS FP4, 1.4 EFLOPS FP8, 31TB HBM4, 1.7 PB/s memory bandwidth, 260 TB/s scale-up, and 43 TB/s scale-out bandwidth.

Su announced that Helios is 'in full production, shipping by the end of Q3,' with customers including OpenAI, Meta, Anthropic, Microsoft Azure, and Oracle. Microsoft will launch HDv2/HXv2 virtual machines and ND MI455X v7 rack instances.

AMD emphasized full open standards—UALoE, Ultra Ethernet, CXL, PCIe 6—avoiding lock-in to NVLink. The ROCm software stack supports PyTorch and ONNX and includes CUDA migration tools.

For physical AI applications like robotics, autonomous driving, and healthcare, AMD unveiled the Ryzen AI Embedded X100 SoC: a single chip integrating 16-core Zen 5, RDNA 3.5 iGPU (40 CUs), and XNDA 2 NPU, with a unified memory architecture. It outperforms Intel Core Ultra 3 by 2.1x in multi-threaded performance and 3.5x in token throughput. AMD also launched the Kria AI SOM and robotics development platform, supporting ROS 2, ROCm, and Xen, enabling over 8,000 real-time control decisions per second and VLA inference under 100ms, targeting Nvidia Jetson T5000 use cases.

With this product lineup, AMD has completed the entire chain from 'CPU (EPYC) → GPU (MI400) → NIC/DPU (Pensando) → rack (Helios) → software (ROCm) → edge (X100/Kria),' differentiating through open standards and modular replaceability, directly challenging NVIDIA's Vera Rubin NVL72 and GB200 ecosystem.

However, Wall Street reacted cautiously, with AMD's stock dropping nearly 5% on Thursday, as investors remain concerned about Helios production yields, HBM4 supply, and whether the promised 30% cost-per-token advantage over NVIDIA will materialize.

Regardless, AMD made a definitive statement on Thursday by delivering 'dual 2nm chips + full-rack AI infrastructure' in one go, signaling that it is no longer just a CPU comeback story, but aims to be a co-definer of infrastructure in the Agentic and Physical AI era.