OpenAI, TSMC, Tesla Are All Betting on Wafer-Scale Chips: The New Frontier in AI Computing Power Race

The next phase of AI competition is no longer just about whose GPU is fastest, but about who can leverage new chip architectures to reduce data movement costs, delivering higher efficiency and lower power consumption. The battlefield is shifting from 'how fast the chip is' to 'how large the chip can be'.

With OpenAI signing a compute procurement contract worth up to $20 billion with startup Cerebras (CBRS-US), and Tesla (TSLA-US), TSMC (2330-TW), and multiple Chinese research institutions announcing progress, the once-dismissed 'wafer-scale chip' concept is rapidly becoming a deliverable, mass-producible industrial reality.

Earlier this year, OpenAI signed a three-year compute procurement agreement with U.S. chip startup Cerebras, covering up to 750MW of computing capacity, with deliveries scheduled through 2028. Market estimates suggest the total contract value could exceed $20 billion.

The significance of this order lies not only in its size, but in elevating 'wafer-scale chips' from a manufacturing technique to a central component of the computing infrastructure landscape.

Cerebras' core product is a revolutionary 'whole wafer' chip that defies traditional packaging logic. Unlike standard chip manufacturing, which cuts a wafer into hundreds of individual dies, Cerebras keeps the entire wafer intact and interconnected, forming a single, massive logic system.

After going public on U.S. stock markets earlier this year, Cerebras reported first-quarter revenue of $193 million, a 94% year-over-year increase, with cloud service revenue surging 178% year-over-year.

Notably, Cerebras is not the only player betting on wafer-scale computing. Tesla has restarted its Dojo 3 training chip project; meanwhile, multiple universities, research institutes, and enterprises in China have unveiled 12-inch wafer-scale prototype machines, multi-chiplet prototypes, and product roadmaps.

Wafer-scale computing is evolving from a high-stakes gamble by a few players into a serious option being evaluated across the industry.

The Bottleneck Isn't Compute—It's 'Moving Data'

To understand why wafer-scale chips are rising, we must return to the real pain point of current AI systems. It's no longer simply insufficient compute power, but the runaway cost of data movement.

When large models operate, massive weights and intermediate computation results must constantly shuttle between compute units and memory units. When systems involve multiple chips working in tandem, this data must also be exchanged and synchronized across chips.

Once data leaves the chip die, it must pass through layers of packaging I/O interfaces, circuit boards, network cards, switch chips, and even optical modules.

The larger the cluster, the higher the proportion of power and cost spent on communication. Newly added compute units become increasingly difficult to translate into proportional real-world performance gains.

In response, the industry has split into two approaches.

The first approach treats the 'rack' as a single computer. NVIDIA's (NVDA-US) GB200 NVL72 integrates 72 GPUs into a single liquid-cooled rack system via NVLink; Huawei's CloudMatrix 384 uses 384 Ascend 910C chips with high-speed interconnects to form a so-called 'super node'.

This path relies on more powerful switch chips, copper cables or fiber optics, and system software to minimize latency when large numbers of independent chips work together.

The second path is the direction chosen by wafer-scale computing: directly shortening the physical distance of data transmission. Data exchanges that once occurred between circuit boards and racks are compressed inside the package or even within the same wafer, replacing meter-scale network transmissions with millimeter-scale interconnects.

The core value of this approach is not cramming in more compute units, but fundamentally reducing the distance and cost of data movement.

Analyses indicate both approaches involve trade-offs. Super nodes benefit from mature software ecosystems and easier hardware scalability and replacement, but must bear higher networking costs. Wafer-scale systems, in contrast, achieve higher bandwidth, lower latency, and better energy efficiency at the cost of highly customized manufacturing, power delivery, cooling, and software development.

Notably, in July this year, AMD (AMD-US) and Cerebras announced a 'disaggregated inference' collaboration. AMD's Helios system handles the compute-intensive pre-filling phase, while Cerebras' wafer-scale engine specializes in the latency-sensitive decoding phase.

Both parties estimate this hybrid setup can increase tokens-per-watt by up to five times compared to using the wafer-scale engine alone, suggesting wafer-scale chips may not need to replace GPUs, but could instead become a dedicated layer in heterogeneous data centers for communication-intensive, latency-sensitive tasks.

A Whole Wafer, or Reassembled Chiplets?

Strictly speaking, the term 'wafer-scale chip' in the industry encompasses two fundamentally different technical paths.

The first ceiling for traditional large chips comes from the maximum area a single exposure in advanced lithography can cover—the so-called 'reticle limit,' around 800 square millimeters. For example, NVIDIA's H100 has a die area of about 814 square millimeters, already approaching this physical boundary.

Historically, the industry packed more transistors through process scaling, but as R&D and manufacturing costs for advanced nodes rise, the industry has turned to chiplets—breaking complex chips into smaller pieces and reassembling them via advanced packaging. Wafer-scale computing, however, expands the system boundary from a single package to nearly the scale of an entire wafer.

### Type 1: Whole Wafer, Single Logic System

This is the approach adopted by Cerebras' wafer-scale engine and the only type currently achieving commercial delivery scale.

After wafer fabrication, instead of cutting into individual dies, the entire wafer is interconnected across exposure fields to form a single, continuously operating logic system.

Cerebras' logic is to solve yield issues first, then control the entire system. The latest WSE-3 uses a 5nm process, spans 46,225 square millimeters, integrates 4 trillion transistors and 900,000 AI cores, with peak compute reaching 125 PFLOPS. In area, it equals dozens of standard reticle fields combined.

This highly integrated approach means Cerebras must control more of the supply chain. Wafer-scale engines cannot be plugged into servers like standard PCIe accelerator cards; the company must also handle wafer-scale packaging, power systems, liquid cooling solutions, full system design, compilers, and cluster software development.

In other words, Cerebras isn't selling just a standard chip, but an entire computing system extending from silicon wafers to cloud services.

### Type 2: Multi-Chiplet Wafer-Scale Systems (Reassembled)

This approach takes the opposite logic: first manufacture, cut, and test individual chiplets, then select only the good dies and reassemble them onto a wafer-scale interconnect platform.

Tesla's Dojo project is the most representative case. Tesla designs the D1 chip, training architecture, and software, while TSMC uses its InFO_SoW (Integrated Fan-Out on Substrate of Wafer) technology to assemble 25 D1 chips into a single 'training tile'.

Compared to Cerebras' method, this approach doesn't require operating a defective whole-logic wafer. Chips can be individually tested after manufacturing, with only good dies selected for integration—greatly reducing front-end manufacturing yield risk and enabling easier mixing of chiplets from different processes and functions.

Following Dojo, TSMC has begun expanding its wafer-scale integration technology from a single customer project to an open, general-purpose foundry platform.

According to TSMC's published technology roadmap, the next-generation SoW-X platform aims to further integrate logic chiplets, HBM high-bandwidth memory, and I/O modules, targeting mass production by 2027.

TSMC emphasizes that SoW-X is not a direct successor to Dojo, but a next-generation wafer-scale platform targeting a broader range of high-performance computing and ASIC customers.

Additionally, there are technologies easily confused with wafer-scale computing, including wafer-level packaging, hybrid bonding, and 3D stacking. While these processes complete redistribution, packaging, or vertical connections at the wafer stage, the final product may still be a normally sized packaged chip.

They are important technological foundations supporting wafer-scale computing, but should not be equated with true wafer-scale computing systems.

The Chinese Contenders: From Papers to Prototypes

Over the past two years, China's progress in wafer-scale computing has been significant. While no commercial system yet matches Cerebras in maturity, the field has clearly moved beyond pure conceptual research.

On the academic side, Tsinghua University's Yin Shouyi, Hu