Aspeed to Showcase Two Next-Generation Platform Technologies at OCP APAC Summit

Aspeed Technology (5274-TW), a leader in remote server management chips (BMC), will showcase two next-generation technological highlights at the OCP APAC Summit: the Open Boot and Management Framework (OBMF) open server management architecture, and the OpenPRoT (Open Platform Root of Trust) platform security architecture.

Aspeed stated that, in collaboration with its ecosystem partners, it will demonstrate live hardware implementations showcasing next-generation data centers' capabilities in high-efficiency management and firmware protection, fully driving innovation within the open server ecosystem.

As cloud computing and AI high-performance computing (HPC) architectures grow increasingly complex, system integration costs and cross-platform software compatibility have become core challenges for data center operations. The OBMF architecture, co-exhibited by Aspeed and its ecosystem partners, emphasizes standardized interfaces to enhance information exchange efficiency between remote BMCs and host platforms, enabling various management functions. This approach reduces platform integration costs while improving software portability and cross-platform compatibility.

At this summit, Aspeed will demonstrate multiple core OBMF features, including the PIROM (I²C) function, which uses standardized access mechanisms to read CPU platform information, providing essential foundational data for platform initialization and system management. It also supports OpenBMC Serial-over-LAN (SOL) remote console functionality, assisting developers with remote debugging and problem analysis, and enables system LED and status signal control via the SGPIO interface, effectively integrating system management methods.

Furthermore, firmware protection for servers is critically important, encompassing a comprehensive security architecture covering device authentication, firmware integrity verification, communication encryption, and supply chain trust. Aspeed’s next-generation security chips will support Post-Quantum Cryptography (PQC), helping data centers prepare early for future cybersecurity challenges in the quantum computing era.

Aspeed Technology is also collaborating with ecosystem partners to demonstrate the SPDM (Security Protocol and Data Model) security authentication process of OpenPRoT based on the AST1060 security chip. OpenPRoT adopts the MCTP architecture, ensuring compatibility across different platforms and further advancing Platform Root of Trust toward openness and standardization.