TSMC's CoWoS Yield Reaches 99%, 14x Reticle Size Mass Production by 2029

AI chips continue to evolve toward larger scale and higher integration, driving rapid expansion in advanced packaging dimensions. TSMC (2330-TW)(TSM-US) Vice President of Advanced Packaging Technology and Services, He Jun, stated on the 11th at OCP APAC that TSMC's 5.5x reticle size CoWoS has entered mass production, with multiple AI customers achieving yields exceeding 98%, and some even reaching 99%. As TSMC advances its CoWoS technology at a pace of one generation per year, it aims to scale up to 14x reticle size by 2029.

He Jun shared that he has been involved in packaging since the 1990s, when the term 'advanced packaging' didn’t even exist. He expressed amazement at the industry’s explosive growth in recent years, noting that CoWoS has become a household technical term in Taiwan. He joked, “Now introducing myself in Taiwan is simple—I’m the CoWoS guy.”

He emphasized that the fundamental driver behind the rapid growth of 3DIC and CoWoS is AI. The nearly insatiable demand for computing power from AI continuously pushes technological limits, forcing TSMC to reconfigure its technology development and volume ramp-up models to accommodate rapid customer product iterations.

As AI chips incorporate more compute dies, HBM, and other chiplets, customer demand for larger advanced packaging areas continues to rise. He Jun noted that TSMC has already entered mass production of 5.5x reticle size CoWoS, which has been validated across multiple AI customer products, achieving stable yields above 98%, with some products reaching 99%.

To support the fast product update cycles of AI customers, TSMC’s R&D team is developing new CoWoS technologies at a pace of one generation per year, continuously breaking through packaging area limits, with plans to reach 14x reticle size by 2029—significantly larger than the current 5.5x size.

The continuous scaling of CoWoS reflects the reality that AI systems can no longer be satisfied by a single large chip. He Jun explained that the chiplet architecture overcomes the reticle size limitations of individual chips while reducing the cost of adopting the latest advanced processes. For example, only compute cores use the most advanced nodes, while I/O and other functions use alternative processes, integrated via advanced packaging.

Beyond cost efficiency, chiplets also enhance system performance and effective yield. He Jun pointed out that as advanced processes continue to scale down, process variation within chips increases. Chiplets offer another dimension for solving this, enabling optimal die pairing through advanced algorithms based on electrical and performance characteristics of different dies, reducing natural component variations and improving overall performance consistency after packaging.

He Jun humorously described managing TSMC’s advanced silicon wafer and packaging manufacturing as “running the world’s largest online matchmaking service.” Customers provide complex algorithms, and TSMC finds the perfect “soulmate” for each die, completing pairing, integration, and delivery through its global manufacturing network.

He Jun also noted that increasing the number of chiplets helps improve average yield, allowing dies that might otherwise be unusable due to performance mismatches to be reused through proper pairing—balancing cost and system performance. This, he emphasized, is a key economic and performance driver behind the rapid development of 3DIC.

Looking ahead, He Jun believes the interposer will evolve beyond mere connectivity, integrating active bridges, integrated voltage regulators (IVR), and silicon capacitors to become a future platform.

Additionally, silicon photonics will become a critical technology for future AI advanced packaging. He Jun noted that while electrons are excellent for computation, photons offer higher energy efficiency for signal transmission. As the demand for high-speed data transfer in AI systems continues to rise, silicon photonics will be a key evolution in advanced packaging.

He Jun stressed that AI is expanding beyond data center training to end devices such as smartphones, PCs, AR/VR, robots, and automobiles. Different systems have varying requirements for performance, power consumption, size, and cost. Therefore, closer co-optimization between chips, packaging, and system design will be essential to sustain AI’s evolution.