TSMC's SoIC Enters High-Growth Phase: A14-on-A14 Stacking Targeted by 2029

AI chips are advancing toward 3D stacking. TSMC (2330-TW)(TSM-US) Vice President of Advanced Packaging Technology and Services, Dr. Rick Hsu, stated on the 11th that SoIC has officially entered a high-growth phase. The company has achieved hybrid bonding with a minimum pitch of 6 micrometers, which is already in mass production. TSMC plans to further advance to a 4.5-micrometer pitch by 2029, enabling A14 logic chips to be directly stacked on top of other A14 logic chips—extending AI chips from the 2D plane into the vertical dimension.

TSMC projects that SoIC production capacity will grow at a compound annual growth rate (CAGR) of over 90% from 2022 to 2027, compared to over 80% CAGR for CoWoS during the same period.

Dr. Hsu emphasized that the demand for computing power in AI continues to surge, and advanced packaging architectures are rapidly evolving. In the future, rather than only expanding package size laterally using CoWoS, multiple chips will be vertically stacked via SoIC and hybrid bonding to further enhance computing density and energy efficiency.

Advanced packaging for AI will simultaneously evolve in two directions: 'going wider and going higher.' CoWoS will overcome the planar limitations of single dies and reticle size, while SoIC will extend vertically through 3D stacking, enabling more computing power to be integrated within a limited footprint using advanced process nodes.

According to Dr. Hsu, SoIC leverages true 3DIC and hybrid bonding to deliver over 50 times higher interconnect density than traditional interconnects, while improving power efficiency by approximately 5 times. This advantage is particularly critical for AI systems, as the power bottleneck is increasingly shifting from on-chip computation to data movement between chips as computational workloads grow.

TSMC aims to reduce data transmission power by minimizing the distance between chips and increasing die-to-die interconnect density, making high-performance 3D integrations such as Logic-on-Logic progressively feasible.

On production progress, Dr. Hsu revealed that TSMC has already introduced 6-micrometer hybrid bonding pitch into high-volume manufacturing since last year, indicating that SoIC has moved beyond R&D or niche applications and has officially entered the era of scalable mass production.

Next, TSMC will continue to shrink the hybrid bonding pitch. Dr. Hsu stated that a 4.5-micrometer pitch technology is expected to be introduced by 2029, further increasing inter-chip I/O density and bandwidth while reducing interconnect power consumption.

Notably, the 4.5-micrometer hybrid bonding will support A14-on-A14 stacking, signifying that 3DIC technology will advance from the traditional integration of logic and memory chips to direct 3D integration of cutting-edge logic-on-logic chips.

Dr. Hsu noted that future AI advanced packaging will still rely on logic chips built on the most advanced process nodes. However, to sustain improvements in energy efficiency, planar process scaling alone is no longer sufficient. Vertical stacking of multiple chips via hybrid bonding is essential to continuously increase computing power per unit area.

At the same time, AI systems will continue to require large amounts of HBM, and the integration between memory and logic chips will deepen. The role of interposers will also evolve from merely providing interconnects to incorporating active bridges, integrated voltage regulators, and capacitors, forming a more comprehensive system-in-package platform.