AI Memory Battlefield! SK Hynix and SanDisk Bet on HBF, Redefining HBM and SSD Architecture

The 2026 Future Memory and Storage Conference (FMS 2026) has concluded, with major players in the memory and storage industry—including SK Hynix (000660KS), SanDisk (SNDKV-US), Kioxia, Marvell Technology (MRVL-US), Microchip Technology (MCHP-US), Micron Technology (MU-US), and Renesas Electronics—virtually all in attendance. While their showcased technologies varied, they collectively addressed one core issue: as AI models continue to expand and computing demands surge, traditional memory and storage architectures are increasingly unable to meet data movement and capacity requirements.

Analysis indicates that the most significant signal from the event was not how much speed or density a single product achieved, but rather that the architectural boundary between HBM and SSD is being redefined.

From High Bandwidth Flash (HBF) and high-density QLC NAND to KV cache pooling and PCIe 6.0 storage, each technology aims to bridge the growing gap between AI computation and data access.

Among these, the HBF standard jointly promoted by SK Hynix and SanDisk may become a pivotal starting point for this architectural transformation.

Five Key Highlights from FMS 2026:

- SK Hynix × SanDisk: HBF High Bandwidth Flash Standard – Up to 512GB capacity; bandwidth ranging from 0.4 to 3.0 TB/s - Kioxia × SanDisk: 10th-Gen 3D QLC Flash – 60% higher density; surpassing 37Gb/mm² - Marvell Technology: Three-Tier KV Cache Architecture – Optical interconnect layer supports 32TB hot KV cache; throughput increased 2–3x - Microchip Technology × Micron: End-to-End PCIe 6.0 Storage – 64GT/s per lane; supports post-quantum encryption - Renesas Electronics: Third-Generation MRDIMM Chipset – Up to 16,000MT/s; 25% bandwidth improvement

SK Hynix and SanDisk Introduce HBF to Bridge the HBM-SSD Gap

AI servers currently face a growing contradiction: HBM offers extremely high bandwidth but faces cost and capacity limitations; SSDs offer large capacity and relatively low cost but cannot deliver HBM-level data transfer speeds.

SK Hynix and SanDisk have chosen to find a new solution between the two. The companies jointly released the world’s first High Bandwidth Flash (HBF) specification through the Open Compute Project (OCP), aiming to leverage the capacity advantages of NAND Flash while significantly enhancing data transfer capabilities.

According to the specification, HBF can reach up to 512GB in capacity using 8- or 16-layer NAND stacking designs. Bandwidth is offered in multiple tiers, covering approximately 0.4TB/s to 3.0TB/s. Connection to processors uses the UCIe high-speed interconnect interface, enabling HBF to potentially connect directly to GPUs or CPUs.

Notably, Google (GOOGL-US) and Tenstorrent have also joined the initiative. This indicates that HBF is not merely a new product concept driven solely by memory manufacturers, but is gaining attention from cloud providers and chip design companies.

If this specification continues to gain industry support, the choice between HBM and SSD may evolve beyond a simple trade-off between speed and cost, gradually forming a more nuanced memory hierarchy.

Kioxia and SanDisk Advance QLC, Achieving Over 37Gb/mm² Density

Beyond establishing new memory tiers, competition over NAND Flash cost and capacity continues.

Kioxia and SanDisk announced their 10th-generation 3D QLC Flash technology, claiming up to a 60% increase in bit density compared to 8th-gen products, surpassing 37Gb/mm², setting a new benchmark for QLC density.

This upgrade uses a 332-layer stacked structure, redesigned chip layout, and integrates “CMOS Bonded to Array” (CBA) technology, where CMOS logic circuits and memory arrays are fabricated separately before wafer bonding.

The companies state that the new architecture enables QLC NAND to achieve an interface speed of 4.8Gb/s for the first time, supporting Toggle DDR 6.0 and Separate Command Address (SCA) protocols. Additionally, the “Power-Isolated Low-Tap Termination” (PI-LTT) scheme further improves I/O data output power efficiency.

For AI and cloud data centers, storage competition involves not only speed but also cost per unit capacity and energy efficiency. Therefore, increasing the storage capacity provided by a single chip remains a crucial direction for reducing overall infrastructure costs.

Marvell Rethinks Data Placement with KV Cache Optimization

As AI inference workloads rapidly grow, KV cache is becoming a significant burden on memory capacity. Large models processing long contexts require storing vast amounts of attention mechanism-related data, placing greater pressure on already limited high-bandwidth memory resources.

Marvell’s proposed solution does not simply pursue the performance of individual storage components but reconfigures KV cache across three levels: server, rack, and cluster.

At the server level, Marvell introduced the Bravera SC6 PCIe 6.0 SSD controller, offering double the performance of its PCIe 5.0 predecessor Bravera SC5, aiming to offload more KV cache to SSDs and free up high-value memory resources like HBM.

At the rack level, Structera X uses CXL to create memory pools, allowing multiple servers to share memory resources and mitigate limitations caused by individual server memory shortages.

For larger clusters, Marvell leverages photonic structures, NICs, and chiplets to build an optical-interconnected shared memory layer, connecting accelerator racks within 50 meters and supporting up to 32TB of “hot” KV cache. The company claims token throughput can increase 2–3x without expanding data center space or power consumption.

Analysis suggests the key insight of this architecture is treating “how far data is from compute units” as a system parameter that can be redesigned.

Microchip and Micron Demonstrate End-to-End PCIe 6.0 Storage

PCIe 6.0 also emerged as a key technical focus at this year’s FMS.

Microchip Technology and Micron jointly demonstrated an end-to-end PCIe 6.0 storage architecture, integrating Microchip’s Switchtec PCIe 6.0 fan-out switch with Micron’s 9650 NVMe SSD.

PCIe 6.0 achieves a per-lane data rate of 64GT/s, double that of PCIe 5.0. Microchip emphasized that to fully realize PCIe 6.0 SSD performance, the entire chain—from processor to switch to storage device—must be upgraded simultaneously.

The Switchtec PCIe 6.0 switch is built on a 3nm process, supporting error isolation, diagnostics, multicast, hardware root of trust, secure boot, and CNSA 2.0-compliant post-quantum cryptography.

Micron positioned the 9650 as a production-ready PCIe 6.0 SSD. Both parties stressed that this architecture supports composable, disaggregated data center designs, enabling independent scaling of compute and storage resources.

Renesas’ MRDIMM Reaches 16,000MT/s, Extending DDR5 Platform

On the server main memory front, Renesas Electronics launched its third-generation DDR5 Multiplexed Rank Buffer Dual In-line Memory Module (MRDIMM) chipset, achieving a maximum server data rate of 16,000MT/s—25% faster than the previous generation.

The solution comprises the third-generation multiplexed register clock driver RRG5013 and multiplexed data buffer RRG5103, paired with power management ICs, SPD Hub, and temperature sensors.

A key feature is that the new solution maintains compatibility with existing DDR5 infrastructure and standard DIMM physical dimensions. For server vendors, this means boosting memory bandwidth doesn’t require a full platform redesign, lowering the barrier to adopting new technology.

The Real Theme of FMS 2026: AI Is Redefining the 'Memory Hierarchy'

From HBF and QLC to KV cache, PCIe 6.0, and MRDIMM, these technologies appear to belong to different markets, but they all address the same underlying challenge: AI computation has become so fast that traditional memory and storage architectures are beginning to act as bottlenecks.