Not Just Broadcom! Google Reportedly Partnering with AMD to Develop 10th-Gen TPU! Wedbush: Could Shake Up Semiconductor Industry

Google is reportedly seeking assistance from AMD (AMD-US) to develop its next-generation Tensor Processing Unit (TPU). If true, Wedbush Securities believes this could become a significant turning point for the semiconductor industry. The market had generally expected Google to continue working with its existing ASIC partners, so if AMD joins Google’s in-house AI chip design efforts, it would not only signal AMD’s deeper entry into the custom AI chip market but also highlight the rapidly rising importance of ASIC design capabilities and intellectual property (IP).

According to market reports emerging this week, Alphabet (GOOGL-US), Google’s parent company, may be collaborating with AMD to develop the 10th-generation TPU. SemiAnalysis reported that AMD could leverage its expertise in CPUs, advanced packaging, and networking connectivity to assist Google in designing the next-generation TPU. However, this collaboration remains unconfirmed, with neither Google nor AMD officially verifying the news.

Matt Bryson, an analyst at Wedbush, stated in a client report that if Google indeed chooses AMD over Broadcom, Marvell Technology (MRVL-US), or Intel (INTC-US), it would be highly significant. He noted that Intel has frequently been mentioned in recent discussions about transitional custom chip projects, so Google’s potential shift to AMD could carry major implications for the semiconductor supply chain.

Bryson emphasized that even as a market rumor, this news underscores two critical trends: first, the increasing value of ASIC (Application-Specific Integrated Circuit) design capabilities; and second, the growing importance of IP blocks. As AI hardware faces constraints from advanced process nodes, packaging, HBM, and data center power, companies that can rapidly integrate diverse IP and chip components may gain a significant competitive edge.

Google has long designed its own TPUs, using them for its AI models and Google Cloud services. In April this year, Google launched its 8th-generation TPU, splitting the product line for the first time into two distinct chips: the TPU 8t for training and the TPU 8i for inference. Google stated these chips are tailored to different computing demands in the era of AI agents and will form a core part of its AI Hypercomputer infrastructure.

The TPU 8t is primarily designed for AI model training. Google claims a single Superpod can integrate up to 9,600 chips, delivering 121 exaflops of computing power and 2PB of shared memory. Google also stated the TPU 8t offers approximately three times the performance of its predecessor, significantly reducing training time for large models.

The TPU 8i, on the other hand, targets low-latency workloads such as inference and reinforcement learning. Google said the chip features 384MB of on-chip SRAM and 288GB of HBM, with inter-chip interconnect bandwidth increased to 19.2Tbps. It also includes a dedicated Collectives Acceleration Engine (CAE), which can reduce certain on-chip latencies by up to fivefold. Google estimates the TPU 8i delivers 80% higher inference performance per dollar compared to the previous generation.

Google’s strategic shift reflects how AI computing demands have evolved beyond mere model training to include real-time inference, AI agents, and reinforcement learning. As AI models begin executing multi-step tasks, systems require not only vast accelerators but also more CPU compute, memory, and high-speed networking—elevating the importance of CPU IP, packaging, and networking technologies.

This is precisely why AMD could play a key role in the next-generation TPU. Market reports suggest AMD not only possesses CPU design capabilities but also has accumulated experience in chiplet design and advanced packaging. Through its MI300 series, AMD has demonstrated the ability to integrate CPUs, GPUs, and high-bandwidth memory on a single platform. Analysts speculate that if Google is indeed seeking AMD’s help, its goal may extend beyond acquiring a single CPU IP block—to leveraging AMD’s expertise in heterogeneous computing and packaging integration to build more complex AI accelerators.

AMD has historically been seen in the AI market primarily as a GPU supplier, with its Instinct series positioned as an alternative to NVIDIA’s (NVDA-US) GPUs. However, if AMD participates in custom ASIC projects like Google’s TPU, its role could expand from a general AI accelerator provider to a custom AI chip design partner, opening up new avenues for business growth.

This potential partnership could also impact Google’s long-standing relationship with Broadcom (AVGO-US) in AI chip development. Google has previously collaborated closely with Broadcom on TPU-related ASIC design and supply chains. If Google brings AMD into the next-generation TPU project, the market will watch closely to see whether Google is diversifying its custom AI chip suppliers or merely introducing new IP and design capabilities for specific functions.

Wedbush specifically noted that Google choosing AMD over Broadcom, Marvell, or Intel does not mean the custom AI chip market is a zero-sum game. On the contrary, amid supply constraints in AI infrastructure, demand for ASIC design capabilities and IP is rising simultaneously. Different companies can still benefit from the AI hardware investment boom by providing specific components, IP, or design services.

Google itself continues to significantly increase its AI infrastructure investments. The company previously announced that its capital expenditures in 2026 are expected to reach $175–185 billion, with over half allocated to cloud and machine learning infrastructure. Google not only develops its own TPUs but also continues to adopt NVIDIA GPUs, indicating that major cloud providers are not relying on a single type of AI chip but are instead using various accelerators to meet training, inference, and other workload demands.

This 'multi-architecture' strategy could become a key trend in the next phase of the AI chip market. Google continues to invest in its in-house TPUs while also using NVIDIA GPUs. If it further incorporates AMD’s CPU, packaging, or ASIC design capabilities, it could evolve into an AI computing platform composed of in-house chips, general-purpose GPUs, and third-party IP.

For AMD, if the collaboration is confirmed, the significance would go beyond securing a chip design contract. It would demonstrate that AMD’s technological capabilities have extended into the custom ASIC platforms of one of the world’s largest AI infrastructure providers. This could elevate AMD’s strategic position in the AI semiconductor supply chain and serve as a reference case for securing future custom chip orders from other major cloud providers.

For Google, bringing in AMD may be a move to address the evolving hardware demands driven by rapidly advancing AI models. Google’s current TPU designs have already begun segmenting workloads into training, inference, and reinforcement learning. In the future, if AI agents require more CPU compute and complex data flow processing, the level of integration between CPUs and accelerators may increase further.

However, there is still no official confirmation from Google or AMD regarding this collaboration. As such, it remains unclear what role AMD would play in the 10th-generation TPU, or what the chip’s specific architecture, process node, launch timeline, or commercial scale might be. At this stage, the clearest takeaway is that the market now views AMD as a potential key partner in Google’s next phase of custom AI chip development.

If the partnership materializes, its impact could extend far beyond a single product. AI chip competition is expanding from GPU compute power to encompass ASICs, CPU IP, chiplets, advanced packaging, high-speed networking, and HBM—essentially, holistic system integration. If Google chooses AMD for its next-generation TPU, it would further prove that the AI hardware market is shifting from 'who has the strongest accelerator' to 'who can fastest integrate a complete computing platform.'