TSMC Breaks Through with A16 Backside Power Delivery: Advancing the Angstrom Race – 10% Faster, 20% Lower Power

According to reports, Taiwan Semiconductor Manufacturing Company (TSMC, 2330-TW) has taken an early lead in the angstrom-level semiconductor process domain. To address the bottleneck caused by traditional chips competing for limited routing space between power and signal lines on the front side, the company has gained an advantage in backside power delivery technology for A16, an advanced process node below 2 nanometers.

Per ETNews, industry insiders revealed on the 18th that TSMC has successfully developed and verified A16, becoming the first in the industry to introduce the 'Super Power Rail' (SPR) backside power delivery architecture in an angstrom-class CMOS platform.

The key to this technological breakthrough lies in A16 retaining the gate density and NanoFlex design flexibility of TSMC’s enhanced N2 process, N2P.

In traditional semiconductor chips, both power interconnects and signal interconnects are placed on the front side of the chip. However, as process nodes continue to shrink, these two increasingly compete for limited routing space, leading to worsening congestion and voltage drops (IR Drop) due to increased resistance.

This has made backside power delivery technology highly valued across the industry. Its core concept involves moving the power delivery network from the front to the back of the chip, freeing up more front-side space for signal routing.

However, past implementations of backside power delivery typically required significant adjustments to transistor layouts and standard cell structures. At more advanced process nodes, switching to backside power often meant abandoning parts of existing standard cell libraries and design methodologies.

What sets TSMC’s A16 apart is its attempt to solve power delivery issues while maximizing compatibility with existing design architectures.

Reports indicate that A16 fully relocates the power path to the back of the chip and uses dedicated vias (VB) to directly connect to the source and drain of transistors. Under this architecture, TSMC makes only minimal adjustments to the gate structure, unit size, and layout area on the front side, thus maintaining compatibility with existing chip designs.

In terms of performance, A16 shows clear improvements over N2P. Under the same power consumption, A16’s computing speed can increase by 8% to 10%; if maintaining the same speed, power consumption can be reduced by 15% to 20%, while chip density improves by 8% to 10%.

Such improvements in performance and energy efficiency are particularly suitable for chips like AI accelerators and high-performance computing (HPC) that have high demands for both computational performance and low power consumption. The A16 process is expected to begin mass production in the fourth quarter of this year.

Regarding commercialization competition in backside power delivery, Intel (INTC-US) currently has an earlier layout, having already integrated its PowerVia technology into the Intel 18A process for mass production.

However, ETNews points out that Intel still needs to adjust its existing cell architecture during testing, including modifying pin counts and widening metal spacing.

Reports also indicate that Samsung Electronics (005930-KS) is pushing to introduce backside power delivery in its SF2 process, potentially adopting a solution similar to Intel’s.

An industry insider stated that this technological breakthrough helps improve efficiency while reducing design burdens for products like AI accelerators—especially critical for chips that must balance energy efficiency and computing performance. In the angstrom-level process era, industry competition is no longer limited to process technology itself; design ecosystems are becoming a key battleground.