Breakthrough Achieved! Samsung's 3D DRAM Becomes 'Wafer-Level LEGO' — Experts: Horizontal Capacitor + GAA + PoC Aim for Low-Voltage, Low-Density New DRAM Cell

South Korea's Samsung Electronics has delivered a milestone achievement in 3D DRAM R&D: its 16-layer vertically stacked VS-DRAM (Vertically Stacked DRAM) has completed chip-level read/write verification. The core innovation lies in reconstructing the 1T1C architecture using a combination of 'horizontal capacitor + GAA cell transistor + Peri-on-Cell bonding,' aiming to shift DRAM scaling from planar miniaturization to Z-axis stacking, thereby sustaining bit density improvements below the 10-nanometer node.

On Thursday (24th), ChipLink reported that traditional DRAM has long relied on shrinking unit cells in the XY direction to boost bit density. However, at sub-10nm nodes, bottlenecks have become increasingly severe: reduced spacing between bitlines and storage nodes causes smaller memory capacitors to compromise retention time and sensing margin; thinner wordlines increase resistance, gradually approaching RC timing limits. To address this, Samsung has adopted a new base architecture featuring horizontal wordlines, vertical bitlines, and horizontal memory capacitors—using vertical stacking to free up lateral space and reducing bitline capacitance via vertical bitlines to improve sensing.

The first core innovation is the so-called 'horizontal capacitor' (Horizontal CAP). Unlike conventional high-aspect-ratio vertical capacitors, the horizontal capacitor does not rely on supporter patterns. Samsung fabricated cylindrical horizontal capacitors within its 16-layer structure and tested them at varying lengths. Results showed that capacitance (Cs) increases nearly linearly with capacitor length, indicating that the '1C' in 1T1C can be compensated by adjusting lateral or Z-axis length. Its controllable lateral recess and gap-fill capability are critical for maintaining data retention in a 3D environment.

The second core is the GAA cell transistor. Samsung has upgraded the VS-DRAM cell from double-gate to Gate-All-Around (GAA), using ultra-thin nanosheet channels to enhance short-channel control and self-aligned isolation between cells. Experimental GAA devices demonstrated steeper subthreshold slopes, higher drive currents, and lower Vth, enabling reduced operating voltage. Leakage current is a major concern in DRAM, and Samsung employed two methods to suppress GIDL (Gate-Induced Drain Leakage): work function engineering forms n+ polysilicon at the drain edge to reduce peak electric field, optimizing junction regions while maintaining drive current; no significant inter-tier drift in Ion/Vth was observed across 16 layers, confirming uniformity through experimental validation.

The third core is PoC and TSDV. Peri-on-Cell places core/peripheral circuits above the memory array, shortening I/O data paths to improve speed and energy efficiency. The process requires two bonding steps: thinning the core/peripheral wafers to approximately 1μm, improving bonding voids via surface treatment, and forming Through-Si-Dielectric-Via (TSDV) in the DTI region for vertical interconnects.

Samsung verified that well isolation remains effective after thinning, with electrical variation in thin-body silicon peripheral transistors controlled within 10%. However, alignment errors between DTI and TSDV directly impact contact resistance and reliability, becoming a key factor for future mass production yield.

Across the industry, 3D DRAM has evolved from concept to a shared battleground among the three major memory makers and logic foundries. Materials related to VLSI 2026 indicate that Samsung’s 16-layer VS-DRAM employs GAA and horizontal capacitors while demonstrating PoC feasibility; SK Hynix focuses on 4F² vertical gate technology, combining bitline shielding, shared back gates, and wafer thinning to reduce cell area while maintaining bonded read/write functionality; Micron positions 3D DRAM, wafer/fusion bonding, novel channel materials, and near-GPU memory as its ten-year expansion roadmap, preparing for post-HBM bandwidth and energy walls.

Analysts note that as DRAM development shifts from line-width scaling to deep etching, thin films, polishing, and hybrid bonding, equipment demand will expand beyond lithography tools toward 3D integration technologies.

For AI and high-performance computing, the value of 3D DRAM lies not in showcasing individual parameters but in trading layer count for area savings, shortening data paths via PoC, and using GAA to suppress leakage and enable low-voltage operation. If future iterations scale beyond 16 layers, they could alleviate the 'memory capacity / bandwidth / power consumption' trilemma faced by large models with long contexts, agents, and inference clusters.

However, three major challenges remain: multi-layer yield for horizontal capacitors and GAA, alignment and thermal management in PoC thin-bonding processes, and the cost curve of 3D DRAM relative to 1c/1d planar DRAM and HBM.

Samsung’s successful 16-layer read/write validation proves that 'stacking DRAM upward' is no longer just a PowerPoint concept—it signifies the formation of a viable path below 10nm. Yet true commercialization depends on stack count, capacitor materials, bonding yield, and customer platform validation.