Is UMC the Dark Horse of the Next AI Wave? Silicon Photonics Mass Production and Two Growth Engines Kick Off – Can You Still Get On Board?

AI infrastructure is expanding beyond advanced computing chips to include high-speed interconnects, power management, and specialty processes. UMC is strengthening its positions in silicon photonics and specialty manufacturing; globally, demand for data center power management chips continues to rise.

By Lü Taide

Latest forecasts indicate that the global AI server shipment volume growth rate for 2026 has been revised upward from approximately 28% to nearly 31%, primarily driven by increased capital expenditures from major cloud service providers and rising demand for rack-level AI systems. As GPU and AI accelerator power consumption continues to climb, AI rack power density is rapidly increasing. For example, the Nvidia GB200 NVL72 consumes about 120kW per rack, with supporting infrastructure designed for up to 132kW. The next-generation platforms are advancing toward 500kW and even 1MW-class racks.

Once power density reaches hundreds of kW or even MW levels, existing data centers face new challenges across their entire power delivery chain—from AC power distribution, UPS, and power supplies to 48V or 54V DC bus bars within racks, and down-conversion to low-voltage GPU cores—particularly in conversion efficiency, copper usage, space utilization, thermal management, and transient load handling. Consequently, 800V high-voltage DC power delivery is emerging as a critical technical direction for next-generation ultra-high-power AI data centers.

AI Demand Fuels New Growth in Mature Processes

As AI server and rack power density increases, the importance of power components such as PMICs and MOSFETs—used in power conversion, regulation, and load-side power delivery—rises accordingly. Manufacturers of the underlying BCD and high-voltage analog specialty processes must deliver on operating voltage, conversion efficiency, reliability, integration capability, cost, and long-term supply stability.

UMC’s BCD process spans both 200mm and 300mm wafers, covering technology nodes from 0.5 microns to 55 nanometers. It supports operating voltages up to 200V and enables integration of analog, digital, and power components, serving applications in DC-DC conversion, battery management, and motor drivers.

In Q2 2026, UMC reported consolidated revenue of NT$68.73 billion, up 12.6% quarter-on-quarter and 17% year-on-year. Gross margin improved from 29.2% in Q1 to 32.5%. Wafer shipments increased by 10.6% sequentially, driving capacity utilization from 79% to 85%. The 22/28nm node accounted for 37% of wafer revenue, up from 34% in Q1, with 22nm alone contributing 17.5%—a record high.

For mature-node foundries, capacity utilization remains a key profitability driver. Wafer fabs are highly capital-intensive, with fixed or semi-fixed costs including facility and equipment depreciation, utility systems, and significant engineering and indirect labor expenses. As utilization climbs from 70–80% toward 90%, additional wafer output helps absorb fixed costs, reducing unit manufacturing costs.

Globally, the top ten foundries’ 8-inch capacity utilization has rebounded from around 80% in 2025 to approximately 88% in 2026, with expectations of nearing 90% in the second half. Foundries are also shifting limited capacity from lower-margin applications like display drivers and CIS sensors toward higher-value PMICs, BCD, and power devices.

UMC’s Dual-Track Expansion: Silicon Photonics Enters Mass Production

As transmission speeds increase and distances extend, traditional electrical interconnects face growing challenges in signal integrity, power consumption, and thermal management. Thus, high-speed interconnects in AI data centers are rapidly transitioning from copper to fiber optics. In this context, silicon photonics has emerged as a key semiconductor technology for next-generation AI high-speed interconnects. Its core concept leverages CMOS-compatible semiconductor manufacturing to integrate previously discrete optical functions into photonic integrated circuits (PICs) on wafers, thereby enhancing bandwidth density, energy efficiency, and scalability of optical interconnects.

UMC has moved from technology development to customer product mass production. In July 2026, UMC and Singapore-based silicon photonics IC designer Silith announced the successful delivery of the first batch of mass-produced PIC wafers. Manufactured at UMC’s 12-inch fab in Singapore, these products support Silith’s 1.6T silicon photonics platform, targeting high-speed optical interconnect needs in AI and hyperscale data centers.

By combining Silith’s silicon photonics architecture with UMC’s SOI wafer manufacturing and process integration expertise, the two companies advanced the platform from development to mass-production readiness in just 18 months, achieving production-grade yield and reliability, and securing certification from major cloud infrastructure customers.

Additionally, by the end of 2025, UMC obtained a license for imec’s iSiPP300 silicon photonics process technology, preparing to build its own 12-inch silicon photonics platform and planning to open it for customer product development starting in 2027. UMC also stated it will integrate silicon photonics with advanced packaging technologies to support higher-integration optical interconnect architectures such as CPO (Co-Packaged Optics) and Optical I/O.

Article authorized by "Investment Insight Weekly Issue 2417".