TSMC Ignites Silicon Photonics Revolution: PIC Capacity to Expand 30x in Three Years, CPO Supply Chain Enters Commercialization Era

As the global AI computing race intensifies, data transmission bandwidth and power consumption have become critical bottlenecks in technological advancement. To meet the demands of next-generation high-performance computing (HPC), TSMC (TSM-US)(2330-TW) is accelerating its deployment of silicon photonics and co-packaged optics (CPO) technologies.

According to the latest market intelligence, TSMC's photonic integrated circuit (PIC) production capacity is entering a 'triple leap' phase. Monthly output is expected to expand more than 30-fold from the current 500 wafers to at least 25,000 wafers by 2028, opening a volume production window for the CPO supply chain.

2026: The Year of Breakout

Analysts indicate that TSMC's PIC capacity expansion roadmap is clear: output will rise to 10,000 wafers in Q2 2026, increase to 15,000 wafers by Q4 2026, and surpass 25,000 wafers by 2028. Based on this trajectory, annual PIC output will surge from the current 4 million units to nearly 194 million units, with estimated annual shipments of actual light engines reaching 48.6 million units.

On the customer side, leading firms such as NVIDIA (NVDA-US), Broadcom (AVGO-US), and AMD (AMD-US) are expected to adopt TSMC's COUPE platform from 2026 to 2027, primarily for high-bandwidth, low-power AI GPUs and data center switches. Subsequently, companies like MediaTek, Marvell, and Ayar Labs are projected to join the mass production platform by 2028, signaling that CPO technology will expand from flagship products into broader ASIC and networking chip markets.

CoPoS Acceleration and the 'From Circle to Square' Transformation

To compete with Intel's (INTC-US) EMIB-T technology, TSMC plans to advance the mass production timeline of its next-generation packaging technology, 'CoPoS' (Chip on Panel on Substrate), to 2028. The core of CoPoS lies in utilizing large-area redistribution layers (RDL) to overcome the reticle size limitations of traditional silicon interposers, enabling ultra-large-scale chip integration.

This technology is driving a 'from circle to square' materials revolution in manufacturing:

Square Silicon Wafers: GlobalWafers and合晶 (HEX) have entered the verification phase. GlobalWafers' 310mm × 310mm square silicon wafers are expected to begin small-volume shipments in Q4 2026.

Glass Substrates and TGV Technology: TSMC is collaborating with Japanese substrate leader Ibiden and Taiwan panel giant Innolux for verification. Innolux is responsible for the critical Through-Glass Via (TGV) process at its Tainan facility, marking a significant cross-industry entry of the display panel sector into the AI packaging supply chain.

Foreign investment research shows that CoPoS technology has already been incorporated into NVIDIA's 'Feynman' GPU architecture roadmap, with the Feynman Ultra version expected to fully adopt this architecture by 2029.

Yield Ramp and Pricing Power

Despite its technological leadership, CPO mass production still faces significant yield challenges. After PIC wafer fabrication, multiple processes such as SoIC integration, optoelectronic testing, and FAU (Fiber Array Unit) coupling are required. Under a scenario where SoIC yield is 50%, the actual terminal shipment volume from 10,000 wafers per month could be reduced to approximately 390,000 units after cumulative losses.

Additionally, TSMC's gross margin in the second half of 2026 may be pressured by the initial production costs of its 2nm process and overseas expansion expenses. However, analysts believe TSMC possesses strong pricing power in advanced processes, with 2nm wafer prices projected to approach $30,000. Price increases are expected to effectively offset cost pressures and sustain profitability.