Cutting AI Chip Costs: New SPHBM4 Standard Launched – 75% Fewer Pins, No Silicon Interposer, 300% Speed Boost

The international semiconductor standards body JEDEC has officially released SPHBM4 (designated JESD330-4), a next-generation high-bandwidth memory (HBM) standard. Built on a novel 'standard package + high-speed narrow interface' architecture, SPHBM4 directly addresses the industry's pain points of high HBM packaging costs and tight advanced packaging capacity in current AI compute chips. It is seen as a pragmatic technological pathway bridging traditional DRAM and top-tier HBM.

At its core, SPHBM4 follows a 'reduce pins, increase speed, change substrate' design philosophy. Compared to traditional HBM4, which requires up to 2,048 data signal pins, SPHBM4 slashes the interface by 75% to just 512 bits wide. Simultaneously, it quadruples the per-pin signaling rate from approximately 11 Gbps to 44 Gbps, compensating for the bandwidth loss.

At the top-tier specification of 46 GT/s, SPHBM4 achieves a theoretical peak bandwidth of approximately 2.944 TB/s. In terms of capacity, it supports 4 to 16 layers of DRAM stacking using 24 Gb or 32 Gb dies, enabling a maximum single-stack capacity of up to 64 GB.

The most critical innovation lies in its packaging approach. Traditional HBM4 requires an expensive silicon interposer to connect with the logic die, heavily relying on advanced packaging capacity such as TSMC's CoWoS. In contrast, SPHBM4 can be directly mounted onto low-cost standard organic substrates, completely eliminating dependence on silicon interposers and cutting-edge packaging technologies. This drastically reduces packaging barriers and costs.

Experts highlight that SPHBM4 holds special significance for China's domestic AI chip industry. For years, China's supply chain has lacked access to CoWoS-level advanced packaging and silicon interposer technologies, creating a bottleneck for high-end AI chip development. SPHBM4 offers a viable path that balances 'acceptable performance, affordable cost, and accessible supply.' Since the standard's disclosure, it has drawn significant attention from Chinese semiconductor manufacturers.

The industry widely believes SPHBM4 is not intended to replace HBM4's flagship status. Instead, under dual pressures of constrained advanced packaging capacity and rising costs, it provides the AI supply chain with a highly flexible new option.