Shift in HBM Packaging Technology: Samsung and SK Hynix Decide Not to Adopt Hybrid Bonding for HBM4

Hybrid bonding, once seen as a major leap in high-bandwidth memory (HBM) packaging technology over the past two years, is now seeing a shift in development pace. With JEDEC recently relaxing HBM4 design specifications, the previously deemed essential new technology has lost urgency. South Korea’s two major memory manufacturers, Samsung and SK Hynix (SKHY-US), have both decided to continue using existing packaging architectures for their HBM4 products, delaying the adoption of hybrid bonding.

According to ZDNet Korea, citing industry sources, both Samsung and SK Hynix have decided not to adopt hybrid bonding for HBM4, with the earliest possible implementation expected in the HBM4E generation.

One industry insider even stated that discussions around 16-layer stacking have clearly cooled down, and even in the HBM4E era, 12-layer stacking may remain the mainstream choice.

The key driver behind this shift is a technical adjustment by JEDEC, the international semiconductor standards body: the height limit for HBM packaging has been expanded from 775 micrometers to 1000 micrometers.

HBM inherently involves stacking multiple DRAM dies, where more layers mean higher capacity and bandwidth, but physical constraints limit package height.

The current mainstream thermocompression bonding process uses tiny metal microbumps between layers. This mature process offers stable yields but consumes vertical space. With 12-layer stacks already approaching the old 775μm limit, moving to 16 or 20 layers was becoming increasingly difficult.

This was precisely hybrid bonding’s key advantage: eliminating microbumps and directly bonding copper-to-copper surfaces allows more layers within the same height and improves thermal performance.

However, JEDEC’s height relaxation has completely changed the landscape. The additional 225μm allows the 'legacy' thermocompression bonding process to meet 12- to 16-layer stacking needs without upgrading. A technology once seen as inevitable has suddenly lost its primary driving force.

Beyond height constraints, hybrid bonding also offered thermal advantages. Traditional processes require insulating filler materials around microbumps, which have poor thermal conductivity—essentially adding a layer of insulation between each DRAM layer, worsening heat dissipation as layer count increases. Hybrid bonding eliminates this step, theoretically offering significantly better thermal efficiency.

However, both Samsung and SK Hynix have developed alternative solutions. Samsung introduced HPB (Heat Path Bridge), adding independent thermal pillars inside the package—like installing multiple 'heat chimneys' into the stacked structure. SK Hynix launched its iHBM solution, embedding electrically insulating thermal silicon elements directly between DRAM layers, claiming over 30% reduction in thermal resistance.

The commonality is clear: without changing the bonding method, both companies enhance thermal performance by adding heat-dissipating components within the package structure, effectively neutralizing hybrid bonding’s unique thermal advantage through alternative engineering approaches.

The real key buyer, NVIDIA, isn’t in a hurry

Memory manufacturers’ technology roadmaps ultimately depend on their largest customer: NVIDIA (NVDA-US). According to ZDNet Korea, NVIDIA has already slowed its timeline for demanding higher-layer-count HBM.

The reason is straightforward. A 16-layer HBM doubles both capacity and bandwidth per chip, but this requires simultaneous upgrades to the GPU’s memory controller and interconnect architecture.

If NVIDIA’s next-generation platform can meet bandwidth demands simply by increasing the number of 12-layer HBM chips, there’s little incentive to push memory makers to adopt riskier, lower-yield, and costlier 16-layer processes.

TSMC’s (2330-TW) SoIC advanced packaging technology further alleviates height pressure from another angle. SoIC enables 3D vertical stacking of GPUs and HBM, making the GPU package itself thicker and thereby freeing up more vertical space for HBM.

In other words, future platform architectures are not tightening HBM’s spatial constraints but relaxing them.

Supply chain impact: Who benefits, who faces pressure

Analysts point out that this delay in technology roadmap has clear implications for the supply chain.

Traditional thermocompression bonding equipment makers are clear winners. South Korea’s Hanmi Semiconductor currently leads the global HBM thermocompression bonding equipment market with a 71.2% share. Every generation delay in hybrid bonding extends its order visibility by at least two years.

Hybrid bonding equipment makers face delayed demand, but the story isn’t over. The Netherlands’ Besi holds about 70% of the global hybrid bonding equipment market. China’s TELC has achieved mass production of wafer-to-wafer hybrid bonding, with related business revenue projected to grow 41.92% in 2025. NAURA has also launched chip-to-wafer hybrid bonding equipment this year.

Since both companies currently derive most growth from the logic chip sector, short-term revenue impact is limited. However, the market narrative of 'imminent explosion' has now shifted to 'long-term trend unchanged, timeline delayed.'

Another emerging market that may be overlooked is thermal interface materials inside the package. Both Samsung’s HPB and SK Hynix’s iHBM point in the same direction: HBM cooling may no longer rely solely on external liquid cold plates. Embedding dedicated thermal conduction elements inside the package could become a new option.

This niche market lacks a clear supplier map today, but the demand direction is already emerging.

Slower isn’t necessarily worse

Analysts argue that from a supply chain perspective, this delay in technology adoption may actually be beneficial.

Hybrid bonding requires nanometer-level planarity alignment of two wafers and direct copper diffusion bonding in a cleanroom environment—the highest yield-risk step in the entire HBM manufacturing process.

If Samsung and SK Hynix had forced hybrid bonding into HBM4, any yield fluctuations in mass production would further strain an already tight HBM supply, the last thing the current AI supply chain can afford.

Stabilizing mass production of 12-layer HBM4 and HBM4E using mature thermocompression bonding first, then deploying hybrid bonding in HBM5E when I/O density doubles from 2048 to 4096 to tackle 16- or 20-layer stacking—this slower rhythm ensures more reliable HBM supply in the near term.

For markets that once viewed hybrid bonding as the 'next CoWoS-level investment theme,' this is undoubtedly a cold shower. But with I/O bandwidth doubling in HBM5E already a confirmed direction, hybrid bonding remains an unavoidable technological hurdle—just not arriving as scheduled in 2026.