Logic Performance Enhanced! Samsung Confirms HBM5 to Adopt 2nm Base Die, Performance Up 50% vs HBM4E

South Korea's Samsung Semiconductor released a new executive interview today (27), further revealing its next-generation HBM technology roadmap.

Joo Jae-heung (pronounced), Head of Technology Development for Samsung Electronics' Foundry Business, clearly stated in the interview that the company plans to introduce a 2nm process to manufacture the base die for the HBM5 generation, aiming to overcome both performance and energy efficiency bottlenecks.

He noted that HBM5's operating speed is expected to increase by more than 50% compared to the current HBM4E, with its base die supporting higher-density Through-Silicon Via (TSV) technology to meet the stringent data throughput demands of future AI and high-performance computing. The choice of the 2nm process for the base die is specifically intended to achieve significant improvements in performance and power consumption at the logic control level.

Looking back at recent developments, Samsung's Vice President of Memory Business Development, Hwang Sang-jun (pronounced), sent similar signals in March this year, indicating that Samsung is actively advancing the integration of advanced processes with memory stacking technologies.

Currently, although Samsung uses a 4nm base die for both the HBM4 and HBM4E generations, there are design differences between the two. Samsung fully leveraged the flexibility of the 4nm process, incorporating high-density, ultra-high-performance components into the HBM4E base die, successfully achieving high-speed operation exceeding 14Gbps per second.

Additionally, through more efficient metal layer arrangements, power consumption has been reduced and heat dissipation paths improved, laying the foundation for HBM5's technological leap.

The market expects that with the adoption of 2nm in HBM5, Samsung will seize a critical technological advantage in the next-generation AI memory race.