Regaining AI Packaging话语权! TSMC Develops 'EMIB-like' Packaging Technology with Unimicron to Counter Intel

According to a report by Cailianshe, the battle for AI chip production capacity is intensifying in the back-end packaging stage. Two sources revealed that TSMC is partnering with Taiwan's leading substrate manufacturer Unimicron to develop an advanced packaging solution that technically competes with Intel's EMIB. Internally referred to as 'EMIB-like technology,' TSMC has initiated preliminary discussions with select clients, though the project remains in early development with no clear mass production timeline. Neither TSMC nor Unimicron has commented.

Packaging was once a routine final step in semiconductor manufacturing. However, AI accelerators require integrating multiple compute dies with HBM memory into a single package, drastically increasing demands for interconnect density and thermal management. As a result, advanced packaging has become one of the most critical capacity bottlenecks across the industry.

TSMC's current CoWoS technology relies on silicon interposers beneath processors and memory to enable high-speed, system-wide interconnects, making it the dominant solution for NVIDIA and Google's AI chips. In contrast, Intel's EMIB takes a different approach—embedding tiny silicon bridges only where high-speed communication between dies is needed, within organic substrates. This eliminates the need for large silicon interposers, reducing cost and complexity while enhancing power delivery and design flexibility for next-generation core architectures.

The report indicates Intel is leveraging this differentiated approach to enter the advanced packaging market. EMIB has already attracted NVIDIA's evaluation for its next-generation processor integrating four GPU dies. It is said that after months of validation, NVIDIA has commissioned Intel to package over 3 million of its self-developed AI processors by 2028.

TSMC CEO C.C. Wei recently stated during an earnings call that current advanced packaging capacity is 'extremely tight' and already constraining customer expansion—effectively opening a window for Intel to poach clients. Even if customers shift only packaging to Intel, it allows Intel to demonstrate technical maturity, strengthen customer relationships, and potentially gain leverage to win future foundry orders.

For TSMC, developing its own 'EMIB-like' technology is both defensive and strategic. It aims to prevent Intel from using packaging advantages to reverse-infiltrate the front-end foundry market, while also meeting customer demands for 'more capacity and more integration options.'

The collaboration with Unimicron is seen as a critical signal. Under the EMIB architecture, substrates must embed silicon bridges and connect upper-layer components. Unimicron's expertise in ABF substrate manufacturing complements TSMC's capabilities on the substrate side, filling a key gap in its packaging ecosystem.

Analysts suggest the AI boom is driving a 'dual-track' packaging strategy: CoWoS maintains dominance in flagship training chips, while EMIB-like solutions and panel-level CoPoS address needs for larger form factors, cost sensitivity, and supply chain diversification. TSMC is not waiting for capacity gaps to empower competitors—the advanced packaging arms race has evolved into a full-stack competition spanning front-end processes and back-end integration.