Google Reportedly Plans to Deploy Up to 15 Million TPUs by 2028, Potentially Surpassing NVIDIA in Scale

Market research reports indicate that Google plans to deploy between 12 million and 15 million ninth-generation Tensor Processing Units (TPU v9) by 2028. If this plan materializes, Google could match or even surpass NVIDIA’s projected shipment volume of data center AI GPUs in the same year, based purely on chip count.

Google began developing its own AI accelerators around a decade ago and has steadily increased TPU deployment in recent years. According to the report, citing supply chain investigations, Google is expected to launch TPU v9 in 2028 with a design incorporating four compute dies, significantly increasing demand for advanced process nodes and packaging capacity—potentially more than doubling compared to 2027 levels.

NVIDIA is estimated to supply approximately 8.2 million data center AI GPUs in 2026, with shipments projected to rise to 12.4 million by 2028. If Google successfully produces 12–15 million TPU v9 chips, its total number of AI accelerators would rival NVIDIA’s output, potentially exceeding it at the upper end.

However, raw chip counts cannot be directly equated with overall computing performance. Whether TPU v9 will match or exceed NVIDIA’s Rubin and Rubin Ultra platforms in real-world performance, power efficiency, and deployment density remains uncertain.

On the supply side, the report suggests Google may struggle to secure sufficient capacity from TSMC alone, necessitating the integration of Intel’s foundry and advanced packaging services as early as 2028 to meet mass production targets.

Over recent months, reports have emerged that after testing Intel’s advanced packaging technologies for several months, Google may outsource the production of over 3 million TPUs to Intel by 2028. However, neither Google nor Intel has officially confirmed this collaboration.

Given that TPU v9 is rumored to use four large compute dies, its design must align with specific packaging architectures. Intel’s EMIB and EMIB-T technologies are incompatible with TSMC’s CoWoS-L, meaning Google would need to develop distinct designs if utilizing both manufacturers’ production and packaging solutions.

If predictions hold true, Google’s annual deployment of in-house AI accelerators could exceed the total number of GPUs NVIDIA supplies to the entire market. Considering Google is also expected to continue purchasing NVIDIA chips, the company could become one of the world’s largest buyers and users of AI accelerators, building an exceptionally large-scale AI computing infrastructure.

This development reflects how major cloud providers are accelerating vertical integration by designing custom silicon tailored to their software, AI models, and data center needs, reducing reliance on general-purpose GPUs.

Nonetheless, Google matching or surpassing NVIDIA in shipment volume does not necessarily weaken NVIDIA’s market dominance. Global AI computing demand continues to grow rapidly, allowing both companies to expand simultaneously. Moreover, NVIDIA plans to introduce its Feynman and Feynman Ultra platforms between 2029 and 2030, further boosting its supply capabilities.

More significant than sheer chip volume competition may be the software ecosystem surrounding Google’s TPU. If Google succeeds in expanding TPU adoption and builds a software toolkit and developer environment capable of challenging CUDA, it could pose a direct long-term threat to NVIDIA’s most critical competitive advantage.