DRAM Scaling Reaches Limit, Samsung, SK Hynix, and Kioxia Spark 3D Memory Stacking Battle

The explosive demand for artificial intelligence (AI) computing power is driving a structural transformation in the memory industry. As DRAM and NAND scaling approach physical limits, Samsung Electronics (KR005930), SK Hynix (000660KS), and Kioxia are turning to 3D stacking and hybrid bonding technologies, signaling that future memory competition will shift from 'process scaling' to a battle of 'chip stacking and advanced packaging.' Those who master nanoscale bonding will emerge as key winners in the new era of AI memory.

With AI large models demanding massive data throughput and storage capacity, traditional semiconductor memory chips are facing their most severe physical limits in decades. The scaling benefits of the planar DRAM's traditional 6F2 cell architecture are nearly exhausted, while single-wafer stacked 3D NAND faces physical barriers such as film stress and current decay.

At the recently unveiled top-tier international semiconductor event, '2026 VLSI Symposium,' global memory giants unveiled their latest architectures, declaring that memory industry competition has fully shifted from traditional 'planar miniaturization' to '3D攻坚 (three-dimensional攻坚).'

In the field of high-speed volatile memory (DRAM), the two Korean giants have revealed distinctly different yet equally critical technological paths:

SK Hynix Breaks Through Planar Limits

To address electromagnetic interference and leakage issues caused by the traditional 6F2 architecture, SK Hynix unveiled its latest vertical-channel 4F2 cell DRAM technology.

This technology reorients the transistor channel vertically, directly connecting it to the capacitor and the intersection of word lines and bit lines.

By employing a 'dual-gate' structure and thin-film silicon channels, it successfully suppresses gate-induced drain leakage (GIDL), improving data retention time. Additionally, a design where adjacent transistors share a back gate reduces crosstalk noise, making it a highly viable transitional solution before fully transitioning to an all-3D architecture.

Samsung Electronics Ushers in the 3D DRAM Era

Samsung, on the other hand, has unveiled its 'VS-DRAM' 3D DRAM architecture for the first time, successfully vertically stacking 16 layers of memory cells.

To solve drive performance issues, Samsung introduced a gate-all-around (GAA) structure and used wafer-level 'Peri-on-Cell' fusion bonding technology to bond the peripheral control circuit wafer with the memory array wafer, then established electrical connections via through-silicon dielectric vias (TSDV), demonstrating robust technical readiness for high-throughput I/O.

NAND Layer War: Kioxia Joins Hands with Sandisk to Target 1,000-Layer Ultra-High Stacking

In the NAND flash memory domain, single-wafer stacking beyond 300 to 400 layers faces severe backlash, including current decay from deep-hole etching and wafer warping.

To address this, Kioxia (Kioxia) and SanDisk (SNDKV-US) jointly unveiled 'multi-wafer hybrid bonding technology' (MSA-CBA).

This approach no longer insists on pushing stacking limits on a single wafer but instead stacks multiple wafers through repeated copper-to-copper (Cu-Cu) hybrid bonding.

First, the control circuit wafer is bonded 'face-to-face' with the first memory wafer. Subsequently, through backside redistribution, second and third memory wafers are stacked 'back-to-face' upward, continuously. This not only successfully verified QLC write stability but also announced a clear technical pathway toward NAND with over 1,000 layers.

Industry Insight: Advanced Packaging and Hybrid Bonding Rise as Memory's New Kings

Industry analysis indicates that the technological presentations at VLSI 2026 reveal a shift in memory chip evolution—from pure 'materials, chemistry, and lithographic scaling' to deep co-design involving 'physical microstructures and advanced bonding and packaging.'

Whether it's Samsung's TSDV dielectric vias or Kioxia's Cu-Cu hybrid bonding, hybrid bonding and wafer-level alignment technologies are no longer just back-end packaging techniques but have become prerequisite conditions for wafer design architecture.

For companies like Samsung and Kioxia to achieve higher-density multi-chip stacking, the key is no longer just process nodes, but the ability to precisely align different wafers at the nanometer level and achieve near-seamless integration through hybrid bonding.

The core of future memory competition will shift from 'who can make circuits smaller' to 'who can stack chips higher and more precisely.' As a result, companies mastering high-precision wafer bonding equipment, wafer thinning, chemical mechanical polishing (CMP) technology, and advanced packaging capabilities are becoming increasingly critical players in the next-generation semiconductor race.