AI Chips Grow Larger, Packaging Shifts to Panel-Level and Optical Interconnect! ASE Reveals Latest Timeline for CPO and Glass Substrate

As AI chip computing power continues to rise, not only are dies growing larger, but package area, Chiplet count, memory bandwidth, and power requirements are also increasing simultaneously, forcing advanced packaging platforms to shift toward panel-level packaging and optical interconnect. ASE Holding (3711) COO Wu Tianyu revealed at today’s (30) earnings call that ASE’s 310×310 mm fully automated panel-level packaging production line is scheduled to begin operations in Q1 2027. CPO (Co-Packaged Optics) may see preliminary, small-scale adoption by the end of this year, but glass substrate will not enter mass production within the next 12 months.

Wu Tianyu stated that AI data centers continue to increase computing density, requiring logic chips and memory to support higher bandwidth, which in turn drives packaging size expansion. To accommodate larger dies and more Chiplets, the industry’s direct response is to adopt larger panels or more complex CoWoS architectures.

310×310 mm Panel-Level Packaging Line to Start Production in Q1 2027

Regarding the highly anticipated progress on panel-level packaging, Wu Tianyu said ASE’s 310×310 mm fully automated production line is scheduled to begin production in Q1 2027.

This solution is not a direct replacement for the advanced packaging technologies developed by foundry partners but rather complementary. Both serve similar customer bases and cover comparable technical specifications in terms of package size, line width, and pitch.

The final choice of packaging solution by customers depends not only on performance but also on available capacity, yield, and speed of mass production. Given the ongoing supply shortage in AI packaging, the current market cannot accommodate just a single technology; instead, multiple viable solutions are needed to jointly alleviate capacity bottlenecks.

CPO to See Initial Adoption by End of 2026, Gathering Bandwidth, Thermal, and Yield Data

In addition to expanding package area, as data transmission speeds increase, traditional electrical signal interconnects are increasingly facing power consumption and bandwidth limitations, making CPO a key next-stage technology for AI systems.

Wu Tianyu stated that CPO may begin preliminary, small-scale adoption by the end of 2026, allowing the market to collect critical data on bandwidth, system performance, thermal improvements, yield, and cost-effectiveness, which will inform decisions on subsequent volume ramp-up.

“The hybrid development of electrical and optical signals is a confirmed direction. The current question is when and how to effectively implement it at the system architecture level,” said Wu Tianyu. While some peripheral optical components have been used for years, integrating optical interconnects closer to the chip or substrate significantly increases technical difficulty—this is why the industry has invested heavily for years but has yet to achieve full-scale mass production.

Regarding the specific CPO services ASE can provide, when meaningful revenue will be generated, and the 2027 business outlook, Wu Tianyu did not provide specific figures. He indicated that the company would wait approximately two more quarters to gather additional mass production and system validation data before making further announcements.

After Optical Interconnect, Power Delivery and Thermal Management Become Next Bottlenecks

Wu Tianyu pointed out that as packaging sizes grow larger and optical interconnects are introduced at different system levels, power delivery will become the next critical challenge. Related technologies are expected to be deployed gradually over the next two to three years.

ASE is also integrating its semiconductor packaging, testing, and EMS business capabilities, extending beyond simple packaging to offer system-level solutions encompassing optical interconnect, power delivery, and thermal management.

The company believes that combining EMS-side capabilities in system assembly, optics, power, and thermal management with packaging-and-test-side expertise in advanced packaging, testing, and heterogeneous integration will enable end-to-end co-design for entire AI systems—recreating the development model that previously expanded SiP (System-in-Package) applications.

Glass Substrate Still Under Verification, No Mass Production in Next 12 Months

Glass substrate is also seen as a potential solution for large-scale AI packaging. Compared to traditional organic substrates, glass materials offer potential in dimensional stability, flatness, and fine-line fabrication, but cost, processing difficulty, reliability, and mass production yield still require validation.

Wu Tianyu stated that ASE’s R&D team is collaborating with substrate suppliers, foundries, and customers to evaluate the technical feasibility and economic benefits of glass substrates.

However, ASE has not yet introduced glass substrate into mass production and will not do so within the next 12 months. In other words, glass substrate remains a mid-to-long-term technology option, while near-term expansion of advanced packaging capacity will continue to rely on existing CoWoS, full-process services, panel-level packaging, and testing capabilities.

Full-Process Customers Cover GPU, CPU, and ASIC

ASE also revealed that its current full-process advanced packaging service portfolio covers GPUs, CPUs, and ASICs. The company has already secured customer and capacity demand for 2027 but needs more time to confirm which information can be disclosed externally.

Wu Tianyu stated that in approximately one to two quarters, ASE will be able to provide further details on next year’s LEAP revenue, full-process and other services, and the composition of packaging and testing businesses. As for the detailed breakdown of GPU, CPU, and ASIC contributions, the company will continue to monitor yield, system performance, and end-market performance.